The transmission of digital data signals over a time division multiplexed (TDM) serial communications link, such as a T1 telecommunications link used to transport digitized telephone signals at a bit rate of 1.544 Mb/s, customarily involves the assembly of successive telephone channels into frames of multiple channels of digital data. For example, a typical DS1 frame contains twenty-four TDM telephone signalling channels, of eight bits per channel, plus a framing bit, for a total of 193 bits per frame. The frames are then assembled into superframes of twelve frames each, so that a respective superframe contains 288 multiplexed telephone channel time slots having an interleaved twelve bit superframe bit pattern of one superframe bit occurring every 193 bits of the superframe.
As diagrammatically illustrated in FIG. 1, a superframe bit pattern is a composite code pattern comprised of successive bits of a first, terminal frame pattern Ft, which are interleaved with a second, signalling frame pattern Fs. The terminal frame pattern Ft consists of an alternating pattern of `1`s and `0`s, and the signalling frame pattern Fs consists of three consecutive zero bits (000) followed by three consecutive one bits (111). Thus, interleaving the two frame patterns Ft and Fs produces the composite superframe bit sequence: 1-0-0-0-1-1-0-1-1-1-0-0.
Prior art schemes to locate a framing bit pattern, in order to effect regeneration of embedded clock signal and synchronize the receiver with the transmitter, so as to allow recovery of the serial data, typically analyze or operate directly upon the transmitted data. For example, the U.S. Patent to Jiang U.S. Pat. No. 4,730,346, which looks for an extended superframe (ESF) pattern, uses a hardware (memory) intensive scheme to load a plurality of successive extended superframes into memory, and then iteratively processes the stored data to find where the extended superframe pattern is located. Additional examples of framing pattern detection mechanisms may be found in the U.S. patents to Graves et al, U.S. Pat. No. 4,622,666, Hoogoveen, U.S. Pat. No. 4,347,606, and Susset, U.S. Pat. No. 3,940,563.
Notwithstanding their processing complexity, a particular shortcoming of such conventional framing pattern detection schemes is the substantial memory redundancy requirement for accommodating a sufficient number of successive frames that will ensure that no potential framing bit locations are missed. While such a brute force approach may be capable of achieving reasonably fast framing recovery, it is hardware intensive and therefore costly.